1. Field of the Invention
This invention relates to a delay circuit and more particularly to a technique to control the delay values of the delay circuit.
2. Description of the Related Art
In general, delay circuits are liable to have variations in delay values due to piece-to-piece variations of devices which constitute the delay circuits and environmental variations when used. Japanese Published Unexamined Patent Application No. 2003-23343 discloses that a first delay circuit detects the required number of delay elements to provide a desired delay time and a second delay circuit controls the number of delay elements by a microcomputer in accordance with the number of the delay elements detected in the first delay circuit in order to obtain the desired delay time. At this time, variations in delay values caused by the piece-to-piece variations of devices and environmental variations can be restrained by the microcomputer control.
However, in the aforementioned patent application, because the number of delay elements in the second delay circuit is controlled in accordance with the number of delay elements in the first delay circuit, i.e, the number of the delay elements is controlled based on data retaining the number of delay elements in advance, incorporation of the microcomputer into the circuit is required and it makes the circuit configuration complicated.
Additionally, when a small delay value is desired and a delay value of a delay element is large for the desired small delay value, since a decrease in the number of delay elements used leads to an increase in delay intervals of each delay element, it is difficult to make an accurate adjustment in delay time and keep the accuracy in delay time.